1. Field of the Invention
This invention relates generally to analog to digital converters (ADCs) and more particularly to an ADC including a dynamic comparator circuit.
2. Description of Related Art
On-chip analog-to-digital converters (ADCs) are currently being utilized for simplifying systems, reducing system power and reducing system weight. CMOS image sensors, moreover, have been widely accepted for visible imaging applications since they enable easy integration of on-chip ADCs. CMOS image sensors typically consist of an array of passive or active pixel sensors (APS) which are particularly adapted for parallel processing. The ADC architecture can consist of one ADC per chip down to one ADC per pixel. The single ADC per chip operates at high speeds while the ADC per pixel operates at the frame rate. A good compromise has been found to have one ADC per column. With such an approach, ADCs are needed which fit in a column's width, in the order of approximately 10 μm, and operate at a row repetition rate.
Sloped or ramped ADCs are also well known in the art and operate at row rates and take up minimal chip area. These converters have been used in conventional CMOS image sensors and can meet the required row rates and lay out area. A sloped ADC uses a single dynamic comparator to compare the input signal voltage level to a ramp voltage signal. Once the ramp voltage passes the amplitude of the input signal, the comparator latches the ramp's count value into one or more memory cells which are later read off the chip in binary fashion.
An inherent limitation of a sloped ADC, however, has been in the comparator. If the ADC is operating at a frequency f, the ADC digitizing time is 1/f. For an N bit ADC, the comparator has 1/[f(2n−1)] seconds for each comparison and hence needs a bandwidth of f(2n−1). Similarly, the gain of the comparator needs to be doubled for each bit of resolution. For each additional bit of resolution, the gain bandwidth product (GBP) of the comparator quadruples, and the ADC begins to require a considerable increase in power. Therefore, for high resolution and fast frame active pixel sensor (APS) arrays, a sloped ADC heretofore has been less appealing. For example, a 600×600 APS array, operating at 30 frames/sec., will have an 18 kHz row rate. Since time is needed to sample and hold the input, the ADC will have a sample rate on the order of 22 kHz. For 12 bits of resolution, the comparator will need to switch at approximately 90 Mhz.
Dynamic comparators, however, have been found to offer a desirable solution to the power problem in that they require only a small area, are fast, and use relatively low power. As such, they become a desirable component in an ADC. High speed and gain can also be achieved by using positive feedback, which is also well known in the art.
Dynamic comparators have a reset time and a latch time. During reset, the input is sampled, while during latch, the comparator swings to predetermined output levels. It is to be noted that power is dissipated only when the clock signal applied switches on or off. Thus, average power Pave is proportional to frequency f, i.e., Pav=CV2f, where f is the switch rate (clock frequency). When desired, some quasi-dynamic comparators use a small amount of bias current to help with the input sampling.